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1 for more information www.linear.com/ltm8062 typical applicat ion features description 32v in , 2a module power tracking battery chargers the lt m ? 8062/ltm8062a are complete 32v in , 2a module ? power tracking battery chargers. the ltm8062/ ltm8062a provide a constant-current/constant-voltage charge characteristic, a 2a maximum charge current, and employ a 3.3v float voltage feedback reference, so any desired battery float voltage up to 14.4v for the ltm8062 and up to 18.8v for the ltm8062a can be programmed with a resistor divider. the ltm8062/ltm8062a employ an input voltage regula - tion loop, which reduces charge current if the input volt - age falls below a programmed level, set with a resistor divider. when the ltm8062/ltm8062a are powered by a solar panel, this input regulation loop is used to maintain the panel at peak output power. the ltm8062/ltm8062a also feature preconditioning trickle charge, bad battery detection, a choice of termination schemes and automatic restart. the ltm8062/ltm8062a are packaged in a thermally en - hanced, compact (9mm 15mm 4.32mm) over-molded land grid array (lga) package suitable for automated assembly by standard surface mount equipment. the ltm8062/ltm8062a are rohs compliant. l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 2a lifepo 4 module battery charger applications n complete battery charger system n input supply voltage regulation loop for peak power tracking in mppt (maximum peak power tracking) solar applications n resistor programmable float voltage up to 14.4v on the ltm8062 and 18.8v on the ltm8062a n wide input voltage range: 4.95v to 32v (40v abs max) n 2a charge current n accommodates li-ion/polymer, lifepo 4 , sla n integrated input reverse voltage protection n user selectable termination: c/10 or termination timer n 0.75% float voltage reference accuracy n 9mm 15mm 4.32mm lga package n industrial handheld instruments n 12v to 24v automotive and heavy equipment n desktop cradle chargers n solar power battery charging charge current vs battery voltage 8062 ta01a ltm8062 gnd v ina v in v inreg run tmr ntc v in 6v to 32v bat bias chrg fault adj 4.7f 274k 2.87m 1-cell lifepo 4 (3.6v) battery voltage (v) 0 0 charging current (ma) 2 2500 8062 ta01b 1 3 4 1000 500 1500 2000 normal charging precondition termination ltm8062/ltm8062a 8062fd
2 for more information www.linear.com/ltm8062 pin configuration absolute maximum ratings v ina , v in ................................................................... 40v v inreg , run, chrg , fa u lt ...................... v in + 0.5, 40v tmr, ntc ................................................................ 2.5v bat (ltm8062) ......................................................... 15v bat (ltm8062a) ...................................................... 20v bias .......................................................................... 10v adj ............................................................................. 5v maximum internal operating temperature (note 2) ................................................................. 125c maximum body solder temperature ..................... 245c (note 1) a b c d e f bank 1 fault adj bias bank 2 bat gnd g h j k l 7 6 5 4 3 2 1 bank 3 bank 4 v in v ina lga package 77-lead (15mm 9mm 4.32mm) top view chrg gnd tmr ntc run v inreg t jmax = 125c, ja = 17.0c/w, jcbottom = 6.1c/w, jctop = 16.2c/w, jb = 11.2c/w, weight = 1.7g values determined per jedec 51-9, 51-12 order information lead free finish tray part marking* package description temperature range ltm8062ev#pbf ltm8062ev#pbf ltm8062v 77-lead (15mm 9mm 4.32mm) lga C40c to 125c ltm8062iv#pbf ltm8062iv#pbf ltm8062v 77-lead (15mm 9mm 4.32mm) lga C40c to 125c ltm8062aev#pbf ltm8062aev#pbf ltm8062av 77-lead (15mm 9mm 4.32mm) lga C40c to 125c ltm8062aiv#pbf ltm8062aiv#pbf ltm8062av 77-lead (15mm 9mm 4.32mm) lga C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ ltm8062/ltm8062a 8062fd
3 for more information www.linear.com/ltm8062 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm8062e/ltm8062ae are guaranteed to meet performance specifications from 0c to 125c internal. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm8062i/ltm8062ai are guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c. run = 2v. the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: this parameter is valid for programmed output battery float voltages 4.2v. for other float voltages, v in start is 3.3v above the programmed output battery float voltage. this parameter is guaranteed by design, characterization, and correlation with statistical process controls. note 4: the maximum bat charging current is reduced by thermal foldback. see the typical performance characteristics for details. parameter conditions min typ max units v in maximum operating voltage 32 v v in start voltage v bat = 4.2v (note 3) 7.5 v v in ovlo threshold v in rising 32 35 40 v v in ovlo hysteresis 1 v v in uvlo threshold v in rising 4.6 4.95 v v in uvlo hysteresis 0.3 v v ina to v in diode forward voltage drop v ina current = 2a 0.55 v maximum bat float voltage ltm8062 ltm8062a 14.7 19.3 v v input supply current standby mode run = 0, v inreg = 15v 85 18 a a maximum bat charging current (note 4) 1.8 2.1 a adj float reference voltage l 3.275 3.25 3.3 3.325 3.34 v v adj recharge threshold voltage threshold relative to adj float reference 82.5 mv adj precondition threshold voltage adj rising 2.3 v adj precondition threshold hysteresis voltage relative to adj precondition threshold 95 mv adj input bias current charging terminated cv operation 65 110 na na v inreg reference voltage adj = 3v, i bat = 1a l 2.61 2.7 2.83 v v inreg bias current v inreg = 2.7v 27 a ntc range limit (high) voltage v ntc rising 1.25 1.36 1.45 v ntc range limit (low) voltage v ntc falling 0.27 0.29 0.315 v ntc disable impedance 250 500 k? ntc bias current v ntc = 0.8v 45 53 a ntc threshold hysteresis for both high and low range limits 20 % run threshold voltage v run rising 1.15 1.20 1.25 v run hysteresis voltage 120 mv run input bias current C10 na chrg, fault output low voltage 10ma load 0.4 v tmr charge/discharge current 25 a tmr disable threshold voltage 0.25 v operating frequency 0.85 1 1.15 mhz ltm8062/ltm8062a 8062fd
4 for more information www.linear.com/ltm8062 typical performance characteristics efficiency vs i b at , 14.4v float efficiency vs i b at , 18.8v float adj float voltage vs temperature i bias vs i b at , 4.2v float i bias vs i b at , 7.2v float i bias vs i b at , 8.4v float efficiency vs i b at , 4.2v float efficiency vs i b at , 7.2v float efficiency vs i b at , 8.4v float t a = 25c, unless otherwise noted. i bat (ma) 0 70 efficiency (%) 72 74 76 1000 84 8062 g01 500 1500 2000 78 80 82 v ina = 12v v ina = 24v i bat (ma) 0 80 efficiency (%) 81 82 83 1000 87 8062 g02 500 1500 2000 84 85 86 v ina = 12v v ina = 24v i bat (ma) 0 81 efficiency (%) 82 83 84 1000 88 8062 g03 500 1500 2500 2000 85 86 87 v ina = 12v v ina = 24v i bat (ma) 0 82 efficiency (%) 83 84 85 1000 90 8062 g04 500 1500 2000 86 87 88 89 v ina = 24v temperature (c) ?50 3.265 adj float voltage (v) 0 3.280 8062 g05 ?25 25 100 125 50 75 3.270 3.275 i bat (ma) 0 0 i bias (ma) 5 10 15 1000 25 8062 g06 500 1500 2000 20 v ina = 12v v ina = 24v i bat (ma) 0 0 i bias (ma) 5 10 15 1000 45 8062 g07 500 1500 2000 20 25 30 35 40 v ina = 12v v ina = 24v i bat (ma) 0 0 i bias (ma) 5 10 15 1000 50 45 8062 g08 500 1500 2000 20 25 30 35 40 v ina = 24v v ina = 12v i bat (ma) 0 86 efficiency (%) 87 88 89 1000 93 8062 g23 500 1500 2000 90 91 92 v ina = 24v ltm8062/ltm8062a 8062fd
5 for more information www.linear.com/ltm8062 typical performance characteristics input current vs i b at , 14.4v float input current vs i b at , 18.8v float i q vs v ina , run = 0v, v inreg open maximum i b at vs adj input current vs i b at , 4.2v float input current vs i b at , 7.2v float input current vs i b at , 8.4v float i bias vs i b at , 14.4v float i bias vs i b at , 18.8v float t a = 25c, unless otherwise noted. i bat (ma) 0 0 i bias (ma) 5 10 15 1000 45 8062 g09 500 1500 2000 20 25 30 35 40 v ina = 24v i bat (ma) 0 0 input current (ma) 100 200 1000 900 800 8062 g10 500 1500 2000 300 400 500 600 700 v ina = 12v v ina = 24v i bat (ma) 0 0 input current (ma) 200 1000 1400 1200 8062 g11 500 1500 2000 400 600 800 1000 v ina = 12v v ina = 24v i bat (ma) 0 0 input current (ma) 200 1000 1600 1400 1200 8062 g12 500 1500 2500 2000 400 600 800 1000 v ina = 12v v ina = 24v i bat (ma) 0 0 input current (ma) 200 1000 1400 1200 8062 g13 500 1500 2000 400 600 800 1000 v ina = 24v v ina (v) 0 0 i q (a) 20 250 200 8062 g14 10 30 40 50 100 150 adj voltage (v) 0 0 maximum i bat (ma) 2 2500 2000 8062 g15 1 0.5 2.5 1.5 3 3.5 500 1000 1500 i bat (ma) 0 input current (ma) 800 1000 1200 2000 8062 g25 600 400 0 500 1000 1500 200 1600 1400 v ina = 24v i bat (ma) 0 0 i bias (ma) 5 10 15 1000 50 45 8062 g24 500 1500 2000 20 25 30 35 40 v ina = 24v ltm8062/ltm8062a 8062fd
6 for more information www.linear.com/ltm8062 typical performance characteristics temperature rise vs i b at , 14.4v float voltage temperature rise vs i b at , 18.8v float voltage v in standby mode current vs temperature temperature rise vs i b at , 7.2v float voltage temperature rise vs i b at , 8.4v float voltage i bat (ma) 0 0 temperature rise (c) 5 1000 30 8062 g19 500 1500 2000 10 15 20 25 v ina = 24v v ina = 12v i bat (ma) 0 0 temperature rise (c) 5 1000 30 8062 g20 500 1500 2000 10 15 20 25 v ina = 12v v ina = 24v i bat (ma) 0 0 temperature rise (c) 5 1000 40 8062 g21 500 1500 2000 10 15 20 25 30 35 v ina = 24v temperature (c) ?50 0 v in standby mode current (ma) 50 6 8062 g22 0 100 1 2 3 4 5 v ina = 24v v ina = 12v t a = 25c, unless otherwise noted. i bat (ma) 0 0 temperature rise (c) 5 10 1000 45 40 8062 g26 500 1500 2000 15 20 25 30 35 v ina = 24v maximum i b at vs v inreg maximum charge current vs temperature temperature rise vs i b at , 4.2v float voltage v inreg (v) 2 0 maximum i bat (ma) 2500 2000 8062 g16 2.5 3 3.5 500 1000 1500 temperature (c) ?40 ?20 0 charge current (ma) 60 2000 1600 1200 8062 g17 0 80 20 40 120 100 400 800 i bat (ma) 0 0 temperature rise (c) 5 1000 25 8062 g18 500 1500 2000 10 15 20 v ina = 12v v ina = 24v minimum v in vs v b at 1.7a load v bat (v) 0 0 v in (v) 10 25 8062 g27 5 15 20 5 10 15 20 ltm8062/ltm8062a 8062fd
7 for more information www.linear.com/ltm8062 pin functions gnd (bank 1, pin l7): power and signal ground return. bat (bank 2): battery charge current output bus. the charge function operates to achieve the final float voltage at this pin. the auto-restart feature initiates a new charging cycle when the voltage at the adj pin falls 2.5% below the float voltage. once the charge cycle is terminated, the input bias current of the bat pin is reduced to minimize battery discharge while the charger remains connected. v ina (bank 3): anode of input reverse protection schottky diode. connect the input power here if input reverse volt - age protection is desired. v in (bank 4): charger input supply. decouple with at least 4.7f to gnd. connect the input power here if no input reverse voltage protection is needed. bias (pin g7): the bias pin connects to the internal power bus. in most cases connect to v bat . if this is not desirable, connect to a power source greater than 2.8v and less than 10v. chrg (pin k7): open-collector charger status output; typically pulled up through a resistor to a reference voltage. this status pin can be pulled up to voltages as high as v in and can sink currents up to 10ma. during a battery charging cycle, chrg is pulled low. when the charge current falls below c/10, the chrg pin becomes high impedance. if the internal timer is used for termina - tion, the pin stays low during the charging cycle until the charge current drops below a c/10 rate, approximately 200ma, even though the charger will continue to top off the battery until the end-of-charge timer terminates the charge cycle. a temperature fault also causes this pin to be pulled low (see the applications information section). ntc (pin h6): battery temperature monitor pin. this pin is the input to the ntc (negative temperature coefficient) thermistor temperature monitoring circuit. this function is enabled by connecting a 10k, b = 3380 ntc thermistor from the ntc pin to ground. the pin sources 50a, and monitors the voltage across the 10k thermistor. when the voltage on this pin is above 1.36v (t < 0c) or below 0.29v (t > 40c), charging is disabled and the chrg and fault pins are both pulled low. if the internal timer termination is being used, the timer is paused, suspending the charging cycle. charging resumes when the voltage on ntc returns to within the 0.29v to 1.36v active region. there is approxi - mately 5c of temperature hysteresis associated with each of the temperature thresholds. the temperature monitoring function remains enabled while thermistor resistance to ground is less than 250k. if this function is not desired, leave the ntc pin unconnected. adj (pin h7): battery float voltage feedback input. the charge function operates to achieve a final float voltage of 3.3v on this pin. the output battery float voltage (v bat(flt) ) is programmed using a resistor divider. v bat(flt) can be programmed up to 14.4v. the auto-restart feature initi - ates a new charging cycle when the voltage at the adj pin falls 2.5% below the float voltage reference. the adj pin input bias current is 110na. using a resistor divider with an equivalent input resistance at the adj pin of 250k compensates for input bias current error. required resistor values to program desired v bat(flt) follow the equations: r 1 = v b a t ( f l t ) ? 2.5 ? 10 5 3 . 3 ( ) r 2 = r 1 ? 2.5 ? 1 0 5 r 1 ? ( 2.5 ? 10 5 ) ( ) r1 is connected from bat to adj, and r2 is connected from adj to ground. fault (pin j7): open-collector fault status output; typi - cally pulled up through a resistor to a reference voltage. this status pin can be pulled up to voltages as high as v in and can sink currents up to 10ma. this pin indicates charge cycle fault conditions during a battery charging cycle. a temperature fault causes this pin to be pulled low. if the internal timer is used for termination, a bad bat - tery fault also causes this pin to be pulled low. if no fault conditions exist, the fault pin remains high impedance (see the applications information section). tmr (pin j6): end-of-cycle timer programming pin. if a timer-based charge termination is desired, connect a capacitor from this pin to ground. full charge end-of cycle time (in hours) is programmed with this capacitor following the equation: t eoc = c timer ? 4.4 ? 10 6 a bad battery fault is generated if the battery does not reach the precondition threshold voltage within one-eighth of t eoc , or: t pre = c timer ? 5.5 ? 10 5 ltm8062/ltm8062a 8062fd
8 for more information www.linear.com/ltm8062 block diagram 8062 bd v ina 8.2h sense resistor 10f (ltm8062) 2.2f (ltm8062a) 0.1f 0.1f run v inreg adj tmr ntc bias adj gnd fault chrg v in bat current mode battery management controller internal compensation 100k pin functions a 0.68f capacitor is often used, which generates a timer eoc at three hours, and a precondition limit time of 22.5 minutes. if a timer-based termination is not desired, the timer function can be disabled by connecting the tmr pin to ground. with the timer function disabled, charging terminates when the charge current drops below a c/10 rate, approximately 200ma. v inreg (pin l6): input voltage regulation reference. the maximum charge current is reduced when this pin is below 2.7v. there is a 100k resistor to gnd. connecting a resis - tor from v in to this pin sets the minimum operational v in voltage. this is typically used to program the peak power voltage for a solar panel. the ltm8062/ ltm8062a servo the maximum charge current required to maintain the programmed operational v in voltage, through maintain - ing the voltage on v inreg at or above 2.7v. if the voltage regulation feature is not used, connect the pin to v in . run (pin k6): precision threshold enable input pin. the run threshold is 1.25v (rising), with 120mv of input hys - teresis. when in shutdown mode, all charging functions are disabled. the precision threshold allows use of the run pin to incorporate uvlo functions. if the run pin is pulled below 0.4v, the ic enters a low current shutdown mode where the v in pin current is reduced to 15a. typical run pin input bias current is 10na. if the shutdown function is not desired, connect the pin to the v in pin. ltm8062/ltm8062a 8062fd
9 for more information www.linear.com/ltm8062 the ltm8062/ltm8062a are complete monolithic, mid- power, power tracking battery chargers, addressing high input voltage applications with solutions that use a minimum of external components. the products can be programmed for float voltages between 3.3v and 14.4v (ltm8062) or between 3.3v and 18.8v (ltm8062a) with just two external resistors, operating under a 1mhz fixed frequency, average current mode step-down architecture. a 2a power schottky diode is integrated within the module charger for reverse input voltage protection. a wide input range allows the operation to full charge from an input voltage up to 32v. a precision threshold on the run pin allows the implementation of a uvlo feature by using a simple resistor network. the charger can also be put into a low current shutdown mode, in which the input supply bias is reduced to only 15a. the ltm8062/ltm8062a employ an input voltage regula - tion loop, which reduces charge current if a monitored input voltage falls below a programmed level at the v inreg pin. there is a 1% 100k resistor to gnd at this pin. when the ltm8062/ltm8062a are powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power. the ltm8062/ltm8062a automatically enter a battery precondition mode if the sensed battery voltage is very low. in this mode, the charge current is reduced to 300ma. once the battery voltage climbs above the internally set precondition threshold (2.3v at the adj pin), the module charger automatically increases the maximum charge current to the full programmed value. the ltm8062/ltm8062a can use a charge current based c/10 termination scheme, which ends a charge cycle when the battery charge current falls to one-tenth the programmed charge current. the ltm8062/ltm8062a also contain an internal charge cycle control timer, for timer-based termination. when using the internal timer, the charge cycle can continue beyond the c/10 level to top-off the battery. the charge cycle terminates when the programmed time elapses, about three hours for a 0.68f timer capacitor. the chrg status pin continues to signal charging at a c/10 or greater rate, regardless of which termination scheme is used. when the timer-based scheme is used, the ltm8062/ltm8062a also support bad battery detection, which triggers a system fault if a battery stays in precondition mode for more than one-eighth of the total programmed charge cycle time. once charging terminates and the ltm8062/ltm8062a are not actively charging, the charger automatically enters a low current standby mode in which supply bias currents are reduced to 85a. if the battery voltage drops 2.5% from the full charge float voltage, the ltm8062/ltm8062a engage an automatic charge cycle restart. the ic also au - tomatically restarts a new charge cycle after a bad-battery fault once the failed battery is removed and replaced with another battery. the ltm8062/ltm8062a contain a bat - tery temperature monitoring circuit. this feature, using a thermistor, monitors battery temperature and will not allow charging to begin, or will suspend charging, and signal a fault condition if the battery temperature is outside a safe charging range. the ltm8062/ltm8062a contain two digital open-collector outputs, chrg and fault, which provide charger status and signal fault conditions. these binary coded pins signal battery charging, standby or shutdown modes, battery temperature faults and bad battery faults. for reference, c/10 and tmr based charg - ing cycles are shown in figures 1 and 2. operation ltm8062/ltm8062a 8062fd
10 for more information www.linear.com/ltm8062 operation figure 1. typical c/10 terminated charge cycle (tmr grounded, time not to scale) figure 2. typical eoc (timer-based) terminated charge cycle (capacitor connected to tmr, time not to scale) 8062 f01 battery voltage battery charge current run chrg fault maximum charge current precondition current c/10 0 amps float voltage recharge threshold precondition threshold 1 0 1 0 0 1 8062 f02 battery voltage battery charge current run chrg fault maximum charge current precondition current c/10 current automatic restart float voltage recharge threshold precondition threshold 1 0 1 0 0 < t eoc /8 t eoc 1 ltm8062/ltm8062a 8062fd
11 for more information www.linear.com/ltm8062 applications information v in input supply the ltm8062/ltm8062a are biased directly from the charger input supply through the v in pin. this pin pro - vides large switched currents, so a high quality low esr decoupling capacitor is recommended to minimize volt - age glitches on v in . 4.7f is typically adequate for most charger applications. reverse protection diode the ltm8062/ltm8062a integrate a high voltage power schottky diode to provide input reverse voltage protec - tion. the anode of this diode is connected to v ina , and the cathode is connected to v in . there is a small amount of capacitance at each end; please see the block diagram. the integrated diode can also be used to block battery discharge leakage paths. the ltm8062/ltm8062a switch and drive circuitry are designed to stand off some reverse voltage from bat to v in , but leakage paths exist that can put a small load on the battery if v in falls below bat. specifically, the run pin has a small bias current and there is a 100k resistor tied to v inreg to gnd. if either of these pins is connected to v in when it is below bat, it can present a small but finite discharge current to the battery. this discharge current may be blocked by the integrated schottky diode if the run and v inreg circuits are tied to v ina . input supply voltage regulation the ltm8062/ltm8062a contain a voltage monitor pin that enables programming a minimum operational volt - age. there is a 1% 100k resistor from v inreg to gnd. connecting a resistor from v in to the v inreg pin enables programming of minimum input supply voltage, typically used to program the peak power voltage for a solar panel. maximum charge current is reduced when the v inreg pin is below the regulation threshold of 2.7v. if the v inreg function is not used, and if the input supply cannot provide enough power to satisfy the requirements of an ltm8062/ltm8062a charger, the input supply voltage for most applications, the design process is straight forward, summarized as follows: 1. look at table 1 and find the row that has the desired input voltage range and battery float voltage. 2. apply the recommended c in and r adj values. 3. connect bias as indicated. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. bear in mind that the maximum output current is limited by junction tempera - ture, the relationship between the input and output voltage magnitude and polarity and other factors. please refer to the graphs in the typical performance characteristics section for guidance. table 1. recommended component values and configuration (t a = 25c) v in range (v)* v b at (v) c in r adj1 top (k?) r adj2 bottom (k?) 6 to 32 3.6 4.7f 1206 x7r 50v 274 2870 6 to 32 4.1 4.7f 1206 x7r 50v 312 1260 6 to 32 4.2 4.7f 1206 x7r 50v 320 1150 6.25 to 32 4.7 4.7f 1206 x7r 50v 357 835 9.5 to 32 7.05 4.7f 1206 x7r 50v 530 464 9.75 to 32 7.2 4.7f 1206 x7r 50v 549 459 11 to 32 8.2 4.7f 1206 x7r 50v 626 417 11.5 to 32 8.4 4.7f 1206 x7r 50v 642 412 12.75 to 32 9.4 4.7f 1206 x7r 50v 715 383 16.5 to 32 12.3 4.7f 1206 x7r 50v 942 344 17 to 32 12.6 4.7f 1206 x7r 50v 965 340 18.25 to 32 13.5 4.7f 1206 x7r 50v 1020 328 19 to 32 14.08 4.7f 1206 x7r 50v 1090 332 19.5 to 32 14.42 4.7f 1206 x7r 50v 1110 328 23 to 32 16.4 4.7f 1206 x7r 50v 1240 312 23.5 to 32 16.8 4.7f 1206 x7r 50v 1270 309 26 to 32 18.8 4.7f 1206 x7r 50v 1420 301 *operating range, v in must be 3.3v above v bat to start. input bulk capacitance is required. ltm8062/ltm8062a 8062fd
12 for more information www.linear.com/ltm8062 figure 3. resistive divider sets minimum v in applications information will collapse. a minimum operating supply voltage can thus be programmed by monitoring the supply through a resistor divider, such that the desired minimum voltage corresponds to 2.7v at the v inreg pin. the ltm8062/ ltm8062a servo the maximum output charge current to maintain the voltage on v inreg at or above 2.7v. programming of the desired minimum voltage is accom - plished by connecting a resistor as shown in figure 3. r i n = 100 v i n ? 270 2 .7 k if the voltage regulation feature is not used, connect the v inreg pin to v in . physically located far from the battery and the added line impedance may interfere with the control loop. case 2: the battery esr is very small or very large; the ltm8062/ ltm8062a controller is designed for a wide range, but some battery packs have an esr outside of this range. case?3: there is no battery at all. as the charger is designed to work with the esr of the battery, the output may oscillate if no battery is present. the optimum esr is about 100m?, but esr values both higher and lower will work. table 2 shows a sample of parts successfully tested by linear technology: table 2 part number description manufacturer 16tqc22m 22f, 16v, poscap sanyo 35svpd18m 18f, 35v, os-con sanyo tpsd226m025r0100 22f, 25v tantalum avx t495d226k025as 22f, 25v, tantalum kemet tpsc686m006r0150 68f, 6v, tantalum avx tpsb476m006r0250 47f, 6v, tantalum avx apxe100ara680me61g 68f, 10v aluminum nippon chemicon aps-150ell680mhb5s 68f, 25v aluminum nippon chemicon if system constraints preclude the use of electrolytic ca - pacitors, a series r-c network may be used. use a ceramic capacitor of at least 22f and an equivalent resistance of 100m?. an example of this is shown in the typical ap - plications section. mppt temperature compensation a typical solar panel is comprised of a number of series- connected cells, each cell being a forward-biased p-n junc - tion. as such, the open-circuit voltage (v oc ) of a solar cell has a temperature coefficient that is similar to a common p-n diode, or about C2mv/c. the peak power point voltage (v mp ) for a crystalline solar panel can be approximated as a fixed voltage below v oc , so the temperature coefficient for the peak power point is similar to that of v oc . panel manufacturers typically specify the 25c values for v oc , v mp , and the temperature coefficient for v oc , making determination of the temperature coefficient for v mp of a typical panel straight forward. the ltm8062/ltm8062a employs a feedback network to program the v in input regulation voltage. manipulation of the network makes for v in v inreg 8062 f03 ltm8062 input supply r in bias pin considerations the bias pin is used to provide drive power for the in - ternal power switching stage and operate other internal circuitry. for proper operation, it must be powered by at least 2.8v and no more than the absolute maximum rat - ing of 10v. in most applications, connect bias to bat. if there is no bias supply available or the battery voltage is below 2.8v, the internal switch requires more headroom from v in for proper operation. please refer to the typical performance characteristics curves for minimum start and running requirements under various battery conditions. when charging a 2-cell battery using a relatively high input voltage, the ltm8062/ltm8062a power dissipation can be reduced by connecting bias to a voltage between 2.8v and 3.3v. output capacitance in many applications, the internal bat capacitance of the ltm8062/ltm8062a is sufficient for proper operation. there are cases, however, where it may be necessary to add capacitance or otherwise modify the output imped - ance of the ltm8062/ltm8062a. case 1: the module is ltm8062/ltm8062a 8062fd
13 for more information www.linear.com/ltm8062 applications information efficient implementation of various temperature compensa - tion schemes for a maximum peak power tracking (mppt) application. as the temperature characteristic for a typical solar panel v mp voltage is highly linear, a simple solution for tracking that characteristic can be implemented using a linear technology lm234 3-terminal temperature sensor. this creates an easily programmable, linear temperature dependent characteristic. in the circuit shown in figure 4, 100v m p 25 c ( ) v i n r e g ? 1 0 0 1 ? 1 0 0 0 0 0 ? 0.0677 v i n r e g ? r s e t ? ? ? ? ? ? ? k r s e t = 1 00 1 tc ? 440 5 + 0. 0 67 7 v i n r e g ? ? ? ? r i n = ? ? ? ? ? ? ? v m p 2 5 c ( ) tc ? 4405 ? v i n r e g ? ? ? k where tc = temperature coefficient (in v/c), and v mp (25c) = maximum power voltage at 25c. figure 4. mppt temperature compensation network v inreg 8062 f04 ltm8062 linear technology lm234 r in v in v in v + v ? r r set as the temperature coefficient for v mp is similar to that of v oc , the specified temperature coefficient for v oc (tc) of C78mv/c and the specified peak power voltage (v mp (25c)) of 17.6v can be inserted into the equations to calculate the appropriate resistor values for the temperature compensation network in figure 4. initially, determine the r set value using the following equation: r s e t = 100 1 ?78m v / c ? 44 0 5 ? ? + 0.0677 2 .7 ? 17.6 ?78m v / c ? 4405 ? 2 .7 ? ? ? ? k ? 4.12k then, r in can be determined using the calculated r set value: r i n = 10 0 ? 1 7 .6v 2.7 ? 1 0 0 1 ? 1000 0 0 ? 0 . 0677 2 . 7 ? 412 0 ? ? ? ? k ? 1400k ? ? ? ? ? ? battery voltage temperature compensation some battery chemistries have charge voltage require - ments that vary with temperature. lead-acid batteries in particular experience a significant change in charge volt - age requirements as temperature changes. for example, manufacturers of large lead-acid batteries recommend a float charge of 2.25v/cell at 25c. this battery float voltage, however, has a temperature coefficient which is typically specified at C3.3mv/c per cell. in a manner similar to the mppt temperature correction outlined previously, implementation of linear battery charge voltage temperature compensation can be accomplished by incorporating a linear technology lm234 into the output feedback network. for example, a 6-cell lead acid battery has a float charge voltage that is commonly specified at 2.25v/cell at 25c, or 13.5v, and a C3.3mv/c per cell tem - perature coefficient, or C19.8mv/c. using the feedback for example, given a common 36-cell solar panel that has the following specified characteristics: open circuit voltage (v oc ) = 21.7v maximum power voltage (v mp ) = 17.6v open-circuit voltage temperature coefficient (v oc ) = C78mv/c ltm8062/ltm8062a 8062fd
14 for more information www.linear.com/ltm8062 applications information figure 5. lead-acid 6-cell float charge voltage vs temperature with a C19.8mv/c temperature coefficient using lm234 with the feedback network network shown in figure 5, with the desired temperature coefficient (tc) and 25c float voltage (v float (25c)) specified, and using a convenient value of 2.4k for r set , necessary resistor values follow the relations: r fb1 = Cr set ? (tc ? 4405) = C2.4k ? (C0.0198 ? 4405) ? 210k r f b 2 = r f b 1 v f l o a t ( 25 c ) + r f b 1 ? ( 0.0674 / r s e t ) v f b - 1 = 210k 13.5 + 210 k ? ( 0.0674 / 2.4 k ) 3.3 - 1 ? 43k ? r fb3 = 250k C r fb1 ||r fb2 = 250k C 210k||43k ? 215k (see the battery float voltage programming section) while the circuit in figure 5 creates a linear tempera - ture characteristic that follows a typical C3.3mv/c per cell lead-acid specification, the theoretical float charge voltage characteristic is slightly nonlinear. this nonlinear characteristic follows the relation: v float = 4 ? 10 C5 (t 2 ) C 6 ? 10 C3 (t) + 2.375 (with a 2.18v minimum) where t = temperature in c. a thermistor-based network can be used to approximate the nonlinear ideal tempera - ture characteristic across a reasonable operating range, as shown in figure 6. figure 6. thermistor-based temperature compensation network programs v float to closely match ideal lead-acid float charge voltage for 6-cell charger temperature (c) ?10 v float (v) 10 50 40 60 0 20 30 8062 f05b 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.3 ?19.8mv/c temperature (c) ?10 v float (v) 10 50 40 60 0 20 30 8062 f06b 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.6 14.4 14.2 14.8 theoretical v float programmed v bat(float) 8062 f06a ltm8062 196k 69k 22k b = 3380 69k bat adj 198k 6-cell lead-acid battery + 8062 f05a ltm8062 linear technology lm234 r fb1 210k r fb2 43k v + v ? r r set 2.4k bat adj r fb3 215k 6-cell lead-acid battery + status pins the ltm8062/ltm8062a report charger status through two open-collector outputs, the chrg and fault pins. these pins can be pulled up as high as v in , and can sink up to 10ma. the chrg pin indicates that the charger is delivering current at greater than a c/10 rate, or one-tenth ltm8062/ltm8062a 8062fd
15 for more information www.linear.com/ltm8062 applications information of the programmed charge current. the fault pin signals bad-battery and ntc faults. these pins are binary coded, as shown in table 3. table 3. status pin state chrg fault status high high not chargingstandby or shutdown mode high low bad-battery fault (precondition timeout/eoc failure) low high normal charging at c/10 or greater low low ntc fault (pause) if the battery is removed from an ltm8062/ltm8062a charger that is configured for c/10 termination, a low amplitude sawtooth waveform appears at the charger output, due to cycling between termination and recharge events. this cycling results in pulsing at the chrg output. an led connected to this pin will exhibit a blinking pat - tern, indicating to the user that a battery is not present. the frequency of this blinking pattern is dependent on the output capacitance. c/10 charge termination the ltm8062/ltm8062a support a low current-based termination scheme, where a battery charge cycle termi - nates when the charge current falls below one-tenth the programmed charge current, or approximately 200ma. this termination mode is engaged by shorting the tmr pin to ground. when c/10 termination is used, an ltm8062/ ltm8062a charger sources battery charge current as long as the average current level remains above the c/10 threshold. as the full-charge float voltage is achieved, the charge current falls until the c/10 threshold is reached, at which time the charger terminates and the ltm8062/ ltm8062a enter standby mode. the chrg status pin fol - lows the charger cycle and is high impedance when the charger is not actively charging. there is no provision for bad-battery detection if c/10 termination is used. timer charge termination the ltm8062/ltm8062a support a timer-based termina - tion scheme, where a battery charge cycle terminates after a specific amount of time elapses. timer termination is engaged when a capacitor (c timer ) is connected from the tmr pin to ground. the timer cycle time span (t eoc ) is determined by c timer in the equation: c timer = t eoc ? 2.27 ? 10 C7 (hours) when charging at a 1c rate, t eoc is commonly set to three hours, which requires a 0.68f capacitor. the chrg status pin continues to signal charging, regard - less of which termination scheme is used. when timer termination is used, the chrg status pin is pulled low during a charge cycle until the charge current falls below the c/10 threshold. the charger continues to top off the battery until timer eoc, when the ltm8062/ltm8062a terminate the charge cycle and enters standby mode. termination at the end of the timer cycle only occurs if the charge cycle was successful. a successful charge cycle occurs when the battery is charged to within 2.5% of the full-charge float voltage. if a charge cycle is not success - ful at eoc, the timer cycle resets and charging continues for another full timer cycle. when v bat drops 2.5% from the full-charge float voltage, whether by battery loading or replacement of the battery, the charger automatically resets and starts charging. preconditioning and bad-battery fault the ltm8062/ltm8062a have a precondition mode, where the charge current is limited to 15% of the maximum charge current, or approximately 300ma. precondition mode is engaged if the voltage on the bat pin is below the precondition threshold, or approximately 70% of the float voltage. once the bat voltage rises above the precondition threshold, normal full-current charging can commence. the ltm8062/ltm8062a incorporate 90mv hysteresis to avoid spurious mode transitions. bad-battery detection is engaged when the internal timer is used for termination (capacitor tied to tmr). this fault detection feature is designed to identify failed cells. a bad-battery fault is triggered when the voltage on bat remains below the precondition threshold for greater than one-eighth of a full timer cycle (one-eighth eoc). a bad-battery fault is also triggered if a normally charging battery re-enters precondition mode after one-eighth eoc. ltm8062/ltm8062a 8062fd
16 for more information www.linear.com/ltm8062 applications information when a bad-battery fault is triggered, the charge cycle is suspended, and the chrg status pin becomes high impedance. the fault pin is pulled low to signal that a fault has been detected. cycling the chargers power or shutdown function initiates a new charge cycle, but the ltm8062/ltm8062a chargers do not require a manual reset. once a bad-battery fault is detected, a new timer charge cycle initiates if the bat pin exceeds the precondition threshold voltage. during a bad-battery fault, a small current is sourced from the charger; removing the failed battery allows the charger output voltage to rise above the preconditioning threshold voltage and initiate a charge cycle reset. a new charge cycle is started by connecting another battery to the charger output. battery temperature fault: ntc the ltm8062/ltm8062a can accommodate battery tem - perature monitoring by using an ntc (negative tempera - ture coefficient) thermistor close to the battery pack. the temperature monitoring function is enabled by connecting a 10k, 3380 ntc thermistor from the ntc pin to ground. if the ntc function is not desired, leave the pin open. the ntc pin sources 50a, and monitors the voltage dropped across the 10k thermistor. when the voltage on this pin is above 1.36v (0c) or below 0.29v (40c), the battery temperature is out of range, and the ltm8062/ ltm8062a trigger an ntc fault. the ntc fault condition remains until the voltage on the ntc pin corresponds to a temperature within the 0c to 40c range. both hot and cold thresholds incorporate 20% hysteresis, which equates to about 5c. if higher operational charging temperatures are desired, the temperature range can be expanded by adding series resistance to the 10k ntc resistor. adding a 909 resistor will increase the effective temperature threshold to 45c, for example. during an ntc fault, charging is halted and both status pins are pulled low. if timer termination is enabled, the timer count is suspended and held until the fault condi - tion is cleared. thermal foldback the ltm8062/ltm8062a contains a thermal fold - back protection feature that reduces charge current as the ic junction temperature approaches 125c. in most cases, on-chip temperatures servo such that any overtemperature conditions are relieved with only slight reductions in maximum charge current. in some cases, the thermal foldback protection feature can reduce charge currents below the c/10 threshold. in applications that use c/10 termination (tmr = 0v), the ltm8062/ltm8062a will suspend charging and en - ter standby mode until the overtemperature condition is relieved. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of ltm8062/ltm8062a integration. the ltm8062/ltm8062a is nevertheless a switching power supply, and care must be taken to minimize emi and ensure proper operation. even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. see figure 7 for a suggested layout. ensure that the grounding and heat sinking are acceptable. figure 7. suggested layout and via placement fault adj bat (optional) v in v ina chrg gnd gnd thermal vias tmr ntc run v inreg c in c bat 8062 f07 ltm8062/ltm8062a 8062fd
17 for more information www.linear.com/ltm8062 applications information 1. place the c in capacitor as close as possible to the v in and gnd connection of the ltm8062/ltm8062a. 2. if used, place the c bat capacitor as close as possible to the bat and gnd connection of the ltm8062/ltm8062a. 3. place the c in and c bat (if used) capacitors such that their ground current flows directly adjacent or underneath the ltm8062/ltm8062a. 4. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8062/ltm8062a. 5. for good heat sinking, use vias to connect the gnd copper area to the boards internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 5. the ltm8062/ltm8062a can benefit from the heat-sinking afforded by vias that connect to internal gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of ltm8062/ltm8062a. however, these capacitors can cause problems if the ltm8062/ltm8062a are plugged into a live input supply (see application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the v in pin of the ltm8062/ltm8062a can ring to more than twice the nominal input voltage, possibly exceeding the ltm8062/ltm8062as rating and damage the part. if the input supply is poorly controlled or the user will be plugging the ltm8062/ltm8062a into an energized supply, the input network should be designed to prevent this overshoot. this can be accomplished by installing a small resistor in series with v in , but the most popular method of controlling input voltage overshoot is to add an electrolytic bulk capacitor to the v in net. this capacitors relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filter - ing and can slightly improve the efficiency of the circuit, though it is physically large. parallel operation if more current is desired, multiple ltm8062/ltm8062as may be paralleled, as shown in the typical applications section. when doing so, bear in mind the following: 1. each ltm8062/ltm8062a adj pin requires 250k input resistance as described in the adj pin function descrip - tion. table 1 gives the recommended resistor network for a single ltm8062/ltm8062a. if using more than one, either apply one network of the appropriate value to each ltm8062/ltm8062as adj pin or apply a single network, each resistor value divided by the number of paralleled ltm8062/ltm8062as and connect all of the adj pins together. 2. tie the bat outputs directly together. apply the same output capacitance to each ltm8062/ltm8062a as if it were used as a single device and not paralleled. 3. the individual ltm8062/ltm8062as may not share current equally as the battery nears the float voltage. thermal considerations the thermal performance of the ltm8062/ltm8062a is given in the typical performance characteristics section. these curves were generated by the ltm8062/ltm8062a mounted to a 58cm 2 4-layer fr4 printed circuit board. boards of other sizes and layer count can exhibit differ - ent thermal behavior, so it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental operating conditions. for increased accuracy and fidelity to the actual application, many designers use fea to predict thermal performance. to that end, the pin configuration section of the data sheet typically gives four thermal coefficients: ltm8062/ltm8062a 8062fd
18 for more information www.linear.com/ltm8062 80421 f08 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance 1. ja : thermal resistance from junction to ambient. 2. jcbottom : thermal resistance from junction to the bot - tom of the product case. 3. jctop : thermal resistance from junction to top of the product case. 4. jb : thermal resistance from junction to the printed circuit board. while the meaning of each of these coefficients may seem to be intuitive, jedec has defined each to avoid confusion and inconsistency. these definitions are given in jesd 51-12, and are quoted or paraphrased below: 1. ja is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module device, the bulk of the heat flows out the bot - tom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3. jctop is determined with nearly all of the component power dissipation flowing through the top of the pack - age. as the electrical connections of the typical module device are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module device and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is mea - sured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. the most appropriate way to use the coefficients is when running a detailed thermal analysis, such as fea, which considers all of the thermal resistances simultaneously. none of them can be individually used to accurately pre - dict the thermal performance of the product, so it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature versus load graphs given in the typical performance characteristics. a graphical representation of these thermal resistances is given in figure 8. figure 8. thermal resistances among module device printed circuit board and ambient environment applications information ltm8062/ltm8062a 8062fd
19 for more information www.linear.com/ltm8062 applications information typical applications 8062 ta02 ltm8062 gnd v ina v in v inreg run tmr ntc v in 9.5v to 32v dc bat bias chrg fault adj 4.7f 549k 459k 2-cell lifepo 4 (2 3.6v) battery (optional electrolytic capacitor) + basic 2a, 2-cell lifepo 4 battery charger with c/10 termination basic 2a, 4-cell li-ion battery charger with c/10 termination the blue resistances are contained within the module device, and the green are outside. the die temperature of the ltm8062/ltm8062a must be lower than the maximum rating of 125c, so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8062/ltm8062a. the bulk of the heat flow out of the ltm8062/ltm8062a is through the bottom of the module and the lga pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, resulting in impaired perfor - mance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. 8062 ta06 ltm8062a gnd v ina v in v inreg run tmr ntc v in 22v to 32v dc bat chrg fault adj bias 4.7f 1.24m 312k external 3.3v 4-cell li-ion (4 4.1v) battery pack (optional electrolytic capacitor) + ltm8062/ltm8062a 8062fd
20 for more information www.linear.com/ltm8062 2a solar panel power manager with 8.4v lithium ion battery pack and 16v peak power tracking three ltm8062s operating in parallel to produce higher charge current 8062 ta03 ltm8062 gnd v ina v in v inreg run tmr ntc v in solar power unit bat bias chrg fault adj 4.7f 642k 412k 499k 2-cell li-ion (2 4.2v) battery ntc 10k b = 3380 (optional electrolytic capacitor) + r1 549k 0.1% c1 22f c4, c5, c6; murata, grm32er7ya106ka12l c1, c2, c3; pos-cap 16tqc22m 12v to 32v gnd r4 459k 0.1% ltm8062ev gnd v ina v in v inreg run ntc bat bias adj chrg fault c6 10f 35v tmr c3 22f c5 10f 35v + r2 549k 0.1% r5 459k 0.1% c4 10f 35v ltm8062ev gnd v ina v in v inreg run ntc bat bias adj chrg fault tmr ltm8062ev gnd v ina v in v inreg run ntc bat bias adj chrg fault tmr 8062 ta05 r3 549k 0.1% r6 459k 0.1% + c2 22f bat 7.2v, 6a gnd + typical applications ltm8062/ltm8062a 8062fd
21 for more information www.linear.com/ltm8062 lga package 77-lead (15mm 9mm 4.32mm) (reference ltc dwg # 05-08-1856 rev a) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. t he total number of pads: 77 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 4.22 ? 4.42 detail b detail b substrate mold cap 0.27 ? 0.37 3.95 ? 4.05 // bbb z z 15 bsc package top view 9 bsc 4 pad 1 corner x y aaa z aaa z detail a 12.70 bsc 1.27 bsc 7.62 bsc l k j h g f e d c b package bottom view 3 pads see notes a 1 2 3 4 5 6 7 detail a 0.635 0.025 sq. 76x s y x eee suggested pcb layout top view 0.000 1.270 1.270 2.540 2.540 3.810 3.810 5.080 5.080 6.350 6.350 3.810 1.270 2.540 0.000 1.270 3.810 2.540 lga 77 0909 rev a pad 1 dia (0.635) 0.9525 1.5875 0.9525 1.5875 4.1275 3.4925 package in tray loading orientation ltmxxxxxx module tray pin 1 bevel component pin ?a1? package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltm8062/ltm8062a 8062fd
22 for more information www.linear.com/ltm8062 table 3. pin assignment table (arranged by pin number) pin name pin name pin name pin name pin name pin name a1 gnd b1 gnd c1 gnd d1 gnd e1 gnd f1 gnd a2 gnd b2 gnd c2 gnd d2 gnd e2 gnd f2 gnd a3 gnd b3 gnd c3 gnd d3 gnd e3 gnd f3 gnd a4 gnd b4 gnd c4 gnd d4 gnd e4 gnd f4 gnd a5 gnd b5 gnd c5 gnd d5 gnd e5 gnd f5 gnd a6 bat b6 bat c6 bat d6 bat e6 bat f6 bat a7 bat b7 bat c7 bat d7 bat e7 bat f7 bat pin name pin name pin name pin name pin name g1 gnd h1 gnd j1 gnd k1 v in l1 v in g2 gnd h2 gnd j2 gnd k2 v in l2 v in g3 gnd h3 gnd j3 gnd k3 v in l3 v in g4 gnd h4 gnd j4 gnd k4 v ina l4 v ina g5 gnd h5 gnd j5 gnd k5 v ina l5 v ina g6 gnd h6 ntc j6 tmr k6 run l6 v inreg g7 bias h7 adj j7 fault k7 chrg l7 gnd package description package photos ltm8062/ltm8062a 8062fd
23 for more information www.linear.com/ltm8062 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 3/11 updated electrical characteristics section updated v inreg (pin l6) description updated block diagram updated operation section updated figures 2, 7 updated applications information updated/added typical applications 3 7 8 8 9, 15 10, 11, 12, 13 18, 22 b 8/11 added ltm8062a parts. reflected throughout the data sheet 1-24 c 12/11 added graph g27 updated typical applications 6 19 d 7/13 correct r w and r set equations 13 ltm8062/ltm8062a 8062fd
24 for more information www.linear.com/ltm8062 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2010 lt 0713 rev d ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm8062 related parts typical application 2a solar panel power manager for charging 2-cell 8.4v lithium-ion battery, featuring three hour charge time and 16v peak power tracking. battery powers two module regulators part number description comments ltm4601/ ltm4601a 12a dc/dc module regulator with pll, output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4601-1 version has no remote sensing ltm4618 6a dc/dc module regulator 4.5v v in 26.5v, 0.8v v out 5v, 9mm 15mm 4.32mm lga ltm4604a 4a low v in dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 9mm 15mm 2.3mm lga ltm4608a 8a low v in dc/dc module regulator 2.7v v in 5.5v, 0.6v v out 5v, 9mm 15mm 2.8mm lga ltm8020 200ma, 36v dc/dc module regulator en55022 class b compliant, fixed 450khz frequency, 1.25v v out 5v, 6.25mm 6.25mm 2.32mm lga ltm8022 1a, 36v dc/dc module regulator adjustable frequency, 0.8v v out 10v, 9mm 11.25mm 2.82mm lga, pin compatible to the ltm8023 ltm8023 2a, 36v dc/dc module regulator adjustable frequency, 0.8v v out 10v, 9mm 11.25mm 2.82mm lga, pin compatible to the ltm8022 ltm8025 3a, 36v dc/dc module regulator 0.8v v out 24v, 9mm 15mm 4.32mm lga ltm8021 500ma, 36v dc/dc module regulator en55022 class b compliant, fixed 1.1mhz frequency, 0.8v v out 5v, 6.25mm 11.25mm 2.82mm lga ltm8042/ ltm8042-1 1a/350ma module led driver 3v v in 30v, v led up to 28v, buck, boost or buck-boost operation 9mm 15mm 2.82mm lga 8062 ta04 ltm8062 ltm8023 gnd v ina v in v inreg run tmr ntc v in solar power unit bat bias chrg fault adj 4.7f 642k 412k 499k 0.68f ltm8021 2-cell li-ion (2 4.2v) battery ntc 10k b = 3380 v out v out ltm8062/ltm8062a 8062fd

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